The present invention relates to a drive circuit based on MOS FETs which can be utilized in high-voltage applications such as vacuum discharge tubes, electroluminescence, ink jet printers, etc.
As a result of developments which have taken place in FET (field effect transistor) technology in recent years, MOS FETs have come into increasing use in high voltage drive circuits. Such circuits have been configured by directly replacing the bipolar transistors, used in the prior art for such circuits, by MOS FETs. In order to reduce the power consumption of such a drive circuit and improve the output waveform, a push-pull output stage of the form shown in FIG. 1 is generally utilized, based on a P-channel MOS FET 4 and an N-channel MOS FET 5. In FIG. 1, numeral 1 denotes an inverter, 2 and 3 are level shifters for shifting the level of the input signal to the appropriate respective gate input levels of the MOS FETs 4 and 5 which are connected in series between a high supply voltage V.sub.H and a low supply voltage V.sub.L. The operation of this circuit will be described in conjunction with the timing chart of FIG. 2. Firstly, when the signal which is applied to the input of the inverter 1 (referred to in the following as the drive input signal) is at the "1" logic level, the output from the inverter 1 will be at the "0" logic level. Thus, the outputs from the level shifters 2 and 3 will be at the "0" logic level. On the other hand, the P-channel MOS FET 4 will be in the ON state at this time, while the N-channel MOS FET 5 will be in the OFF state. (In the following description and in the appended claims, the term "OFF" state of an FET has the significance of a condition of conduction between the drain and source electrodes of the FET, while the term "OFF" state of an FET has the significance of a condition of substantially non-conduction between the drain and source electrodes). As a result, the output from the drive circuit will be at the V.sub.H potential.
If the drive input signal goes to the "0" logic level, then the output from the inverter 1 will go to the "1" logic level, so that the output from the level shifters 2 and 3 will go to the "1" logic level. The P-channel MOS FET 4 is thereby set in the OFF state, while the N-channel MOS FET 5 is set in the ON state, so that the output from the drive circuit will be at the V.sub.L potential. It is necessary that the voltage difference (V.sub.H -V.sub.L) be lower than the OFF-state withstand voltage of each of the FETs 4 and 5.
In general, an ON-state drain-to-source withstand voltage and an OFF-state withstand voltage are separately specified for the type of FET utilized in such a high voltage drive application, with the ON-state withstand voltage being lower than then OFF-state withstand voltage. If the circuit is used in a status in which the applied voltage of the drive circuit (V.sub.H -V.sub.L) satisfies the condition:
ON-state withstand voltage&lt;(V.sub.H -V.sub.L)&lt;OFF-state withstand voltage,
(where "withstand voltage" of course denotes a minimum value of withstand voltage of the two FETs) then the following problem may arise for the drive circuit of FIG. 1. When the input signal changes from the "0" logic level to the "1" logic level, the P-channel MOS FET 4 changes from the OFF to the ON state, while the N-channel MOS FET 5 changes from the ON to the OFF state. Thus, at a certain instant, both FET 4 and FET 5 may be simultaneously in the ON state. At that instant, the applied voltage (V.sub.H -V.sub.L) will be higher than the ON-state withstand voltage, so that destructive voltage breakdown of FETs 4 and 5 may occur. A similar condition occurs when the input signal changes from the "1" logic level to the "0" logic level.